Method for analyzing defect of SRAM cell

Details Method for analyzing defect of SRAM cell Method for analyzing defect of SRAM cell

2007-12-25

2007-12-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S154000

Reexamination Certificate

active

11486805

ABSTRACT:
Disclosed is a method for analyzing a defect of a semiconductor device, and more particularly a method for electrically analyzing a defect of a transistor formed in a cell having a latch structure, such as SRAM or a sense amplifier of DRAM. The defect analyzing method according to the present invention comprises the steps of forming a test SRAM cell array in a scribe lane region of a wafer which is formed with a plurality of SRAM chips, forming a pad portion for testing the SRAM cell array on the scribe lane region, and applying a predetermined test voltage to the SRAM cell array through the pad portion. The respective array cells constituting the SRAM cell array are provide with two word lines, and individual test voltages can be applied through the pad portion to the two word lines, respectively.

REFERENCES:
patent: 5361232 (1994-11-01), Petschauer et al.
patent: 5568435 (1996-10-01), Marr
patent: 6081465 (2000-06-01), Wang et al.
patent: 6392941 (2002-05-01), Churchill
patent: 6757205 (2004-06-01), Salters

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