Methods of manufacturing multi-level metal lines in...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S072000, C438S622000, C438S623000, C438S624000, C438S625000, C438S626000, C438S629000, C438S636000, C438S648000, C438S656000, C438S672000, C438S675000, C257S758000, C257S759000, C257S760000, C257S762000, C257S763000, C257S764000, C257S765000, C257S766000, C257S767000, C257S768000

Reexamination Certificate

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11027035

ABSTRACT:
Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and second metal layers; forming first and second metal layer pattern by patterning the first metal layer, the etching stopper layer, and the second metal layer, wherein the first metal layer pattern is formed as a lower metal line; forming a connection contact in form of a plug by selectively etching the second metal layer pattern until the etching stopper layer is exposed; forming an interlayer insulating layer to cover the connection contact and the first metal layer pattern; and exposing an upper surface of the connection contact by planarizing the interlayer insulating layer.

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patent: 6133145 (2000-10-01), Chen
patent: 6376361 (2002-04-01), Chooi et al.
patent: 6939794 (2005-09-01), Yin et al.
patent: 7008869 (2006-03-01), Han
patent: 2004/0137719 (2004-07-01), Jin
patent: 2004/0157462 (2004-08-01), Hillyer et al.
patent: 08-111460 (1996-04-01), None
patent: 10-172971 (1998-06-01), None

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