Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-11
2007-12-11
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11062594
ABSTRACT:
In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit forms a floor plan for arranging a plurality of circuit blocks including a non-rectangular area into the chip. A layout processing unit divides each of a plurality of non-rectangular circuit blocks having non-rectangular areas into a plurality of rectangular areas and arranges them into the chip so as to be adapted to the floor plan. A wiring processing unit mutually wires the plurality of circuit blocks. The non-rectangular area is constructed by a set of a plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of the plurality of division rectangular areas. The non-rectangular areas are also introduced with respect to the cells which are arranged in the circuit block.
REFERENCES:
patent: 4777606 (1988-10-01), Fournier
patent: 5341383 (1994-08-01), Shikatani et al.
patent: 5742086 (1998-04-01), Rostoker et al.
patent: 5808898 (1998-09-01), Kajitani et al.
patent: 5870312 (1999-02-01), Scepanovic et al.
patent: 6002857 (1999-12-01), Ramachandran
patent: 6014507 (2000-01-01), Fujii
patent: 6049659 (2000-04-01), Matsumoto et al.
patent: 6080206 (2000-06-01), Tadokoro et al.
patent: 6378121 (2002-04-01), Hiraga
patent: 6584603 (2003-06-01), Shibuya
patent: 6779167 (2004-08-01), Igarashi et al.
patent: 6831356 (2004-12-01), Terada et al.
patent: 6859916 (2005-02-01), Teig et al.
patent: 7222322 (2007-05-01), Chyan et al.
patent: 2002/0162079 (2002-10-01), Igarashi et al.
patent: 2003/0212976 (2003-11-01), Drumm
patent: 2004/0019862 (2004-01-01), Li et al.
patent: 2004/0243964 (2004-12-01), McElvain et al.
patent: 5-160375 (1993-06-01), None
patent: 5-181936 (1993-07-01), None
patent: 5-243383 (1993-09-01), None
patent: 6-124321 (1994-05-01), None
patent: 9-147009 (1997-06-01), None
patent: 10-189746 (1998-07-01), None
patent: 2003-303217 (2003-10-01), None
Curatelli, F et al. “An algorithm for the definition of routing regions in VLSI design” Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on Aug. 12-14, 1990 pp. 184-187, vol. 1 □□.
Do Thuan
Levin Naum
Staas & Halsey , LLP
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