Layout verification based on probability of printing fault

Details Layout verification based on probability of printing fault Layout verification based on probability of printing fault

2007-12-25

2007-12-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11194357

ABSTRACT:
Methods and apparatus for checking layouts of circuit features are provided. In one aspect, a method of designing a layout for a circuit feature is provided that includes deriving a function which relates a size and a plurality of aerial image parameters of the circuit feature to a probability of a printing fault in using a lithographic process to pattern the circuit feature. A layout for the circuit feature is created. The function is used to determine a probability of a printing fault in using the lithographic process to pattern the circuit feature and adjust the layout of the circuit feature as necessary in view of the determined probability of printing fault.

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