Method for synchronizing a cache memory with a main memory

Details Method for synchronizing a cache memory with a main memory Method for synchronizing a cache memory with a main memory

2007-02-20

2007-02-20

Bragdon, Reginald (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C711S143000

Reexamination Certificate

active

10857617

ABSTRACT:
Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

REFERENCES:
patent: 4319079 (1982-03-01), Best
patent: 4573119 (1986-02-01), Westheimer
patent: 4700330 (1987-10-01), Altman et al.
patent: 5045996 (1991-09-01), Barth et al.
patent: 5081675 (1992-01-01), Kittirutsunetorn
patent: 5146603 (1992-09-01), Frost
patent: 5481610 (1996-01-01), Doiron et al.
patent: 5630166 (1997-05-01), Gamache et al.
patent: 6009498 (1999-12-01), Kumasawa et al.
patent: 6014728 (2000-01-01), Baror
patent: 6092172 (2000-07-01), Nishimoto
patent: 6157999 (2000-12-01), Rossbach et al.
patent: 6745294 (2004-06-01), Wilson et al.
patent: 199 57 810 (2000-09-01), None
patent: 0 319 647 (1989-06-01), None
patent: 0 347 040 (1989-12-01), None
patent: 0 583 140 (1994-02-01), None
patent: 0 720 098 (1996-07-01), None
patent: 0 752 662 (1997-01-01), None
patent: 0 439 325 (1999-05-01), None
patent: WO-99/28887 (1999-06-01), None
patent: WO-01/53931 (2001-07-01), None
patent: WO-02/056184 (2002-07-01), None
Motorola M68040 User's Manual, Motorola Inc., 1990.

Affiliated with

Also associated with

Rating

Method for synchronizing a cache memory with a main memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for synchronizing a cache memory with a main memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for synchronizing a cache memory with a main memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3835007