Method for verifying a circuit design by assigning numerical...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

11152472

ABSTRACT:
A method for verifying a circuit design includes a step of assigning numerical values 1/aito input ports of the circuit design according to a function ai+1=(ai−1)2+1, wherein i represents the number of the input port and the numerical value a1is not equal to 2 or 1. Preferably, a1is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l's probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.

REFERENCES:
patent: 6212669 (2001-04-01), Jain
Ilker Hamzaoglu and Janak H. Patel, “New Techniques for Deterministic Test Pattern Generation”, Journal of Electronic Testing: Theory and Applications, Aug.-Oct. 1999, pp. 63-73, vol. 15 , Issue 1-2, Kluwer Academic Publishers Norwell, MA, USA.
Vishwani D. Agrawal and David Lee, “Characterisic Polynomial Method for Verification and Test of Combinational Circuits”, 9th International Conference on VLSI Design, Sep. 1996 vol. 00, p. 341, IEEE, Washington D.C.
Jawahar Jain et. al., “Probabilistic Design Verification”, Proc. Intl Conf. Computer-Aided Design, 1991, pp. 468-471.
Sarangan Krishna Kumar and Melvin A. Breuer, “Probabalistic Aspects of Boolean Switching Functions via a New Transform”, Journal of the Association for computing Machinery, Jul. 1981, pp. 502-520, vol. 28, No. 3, Association for Computing Machinery, New York NY.

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