Semiconductor device and manufacturing method of the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S678000, C257S750000, C257S762000, C257S769000, C257S770000, C257S779000, C257SE23001

Reexamination Certificate

active

11281502

ABSTRACT:
In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the semiconductor chip and the lead terminals are connected by Pb-free connection parts each having a configuration of connection layer/stress buffer layer/connection layer. In each connection part, the connection layer is formed of an inter-metallic compound layer having a melting point of 260° C. or higher or Pb-free solder having a melting point of 260° C. or higher, and the stress buffer layer is formed of a metal layer having a melting point of 260° C. or higher and having a function to buffer the thermal stress.

REFERENCES:
patent: 4984051 (1991-01-01), Yoshida
patent: 6215185 (2001-04-01), Kikuchi et al.
patent: 7193319 (2007-03-01), Sasaki et al.
patent: 2000-223634 (2000-08-01), None

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