Plural bank semiconductor memory device with increased...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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Details

C365S210130

Reexamination Certificate

active

11267805

ABSTRACT:
A semiconductor memory device includes a memory cell array, and first and second boosting voltage generating portions. The first boosting voltage generating portion generates a first driving signal when the semiconductor device operates in an active mode and supplies a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal. The second boosting voltage generating portion includes a first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal and a second boosting voltage generator pumping the boosting voltage in response to the first driving signal when first memory cell array blocks are selected and pumping the boosting voltage in response to the second driving signal when second memory cell array blocks are selected.

REFERENCES:
patent: 6038178 (2000-03-01), Oh
patent: 6128235 (2000-10-01), Jung
patent: 6172931 (2001-01-01), Cha et al.
patent: 7154785 (2006-12-01), Roohparvar
patent: 2001/0050867 (2001-12-01), Song
patent: 2002-015566 (2002-01-01), None
patent: 2000-0014222 (2000-03-01), None
patent: 2003-0057724 (2003-07-01), None

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