Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-10-23
2007-10-23
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S104000, C711S005000, C365S189040, C365S189030, C365S189011, C365S233100
Reexamination Certificate
active
11681384
ABSTRACT:
An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.
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Abhyankar Abhijit M.
Barth Richard M.
Davis Paul G.
Gasbarro James A.
Hampel Craig E.
Bataille Pierre-Michel
Morgan & Lewis & Bockius, LLP
Rambus Inc.
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