Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-08-14
2007-08-14
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S662000
Reexamination Certificate
active
11039429
ABSTRACT:
An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening. We perform a bitline contact plug implant to from a doped contact region under the opening. We activate the doped contact region to form an activated doped contact region using a laser irradiation process. The laser irradiation process improves the electrical activation of the doped contact region without interfering with the silicide and S/D regions of the logic devices.
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Chong Yung Fu
Hsia Liang Choo
Sohn Dong Kyun
Chartered Semiconductor Manufacturing Ltd
Goodwin David
Stoffel William J.
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