Thin film integrated circuit and method for manufacturing...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257SE21415

Reexamination Certificate

active

11110918

ABSTRACT:
A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer. In the second annealing, a base metal film absorbs and accumulates heat of the laser irradiation, and a semiconductor layer is supplied with heat of the base metal film in addition to heat of the laser irradiation, thereby enhancing efficiency of the silicide reaction in the source and drain regions.

REFERENCES:
patent: 5403772 (1995-04-01), Zhang et al.
patent: 5426064 (1995-06-01), Zhang et al.
patent: 5576556 (1996-11-01), Takemura et al.
patent: 5595944 (1997-01-01), Zhang et al.
patent: 5639698 (1997-06-01), Yamazaki et al.
patent: 5644147 (1997-07-01), Yamazaki et al.
patent: 5648277 (1997-07-01), Zhang et al.
patent: 5757456 (1998-05-01), Yamazaki et al.
patent: 5807770 (1998-09-01), Mineji
patent: 5814540 (1998-09-01), Takemura et al.
patent: 5818070 (1998-10-01), Yamazaki et al.
patent: 5834327 (1998-11-01), Yamazaki et al.
patent: 5897347 (1999-04-01), Yamazaki et al.
patent: 5923968 (1999-07-01), Yamazaki et al.
patent: 5956579 (1999-09-01), Yamazaki et al.
patent: 5962897 (1999-10-01), Takemura et al.
patent: 5986286 (1999-11-01), Yamazaki et al.
patent: 6074900 (2000-06-01), Yamazaki et al.
patent: 6118502 (2000-09-01), Yamazaki et al.
patent: 6218678 (2001-04-01), Zhang et al.
patent: 6355512 (2002-03-01), Yamazaki et al.
patent: 6369410 (2002-04-01), Yamazaki et al.
patent: 6455875 (2002-09-01), Takemura et al.
patent: 6475839 (2002-11-01), Zhang et al.
patent: 6512246 (2003-01-01), Tanabe
patent: 6596571 (2003-07-01), Arao et al.
patent: 6605496 (2003-08-01), Yamazaki
patent: 6613614 (2003-09-01), Yamazaki et al.
patent: 6617612 (2003-09-01), Zhang et al.
patent: 6624477 (2003-09-01), Takemura et al.
patent: 6670640 (2003-12-01), Yamazaki et al.
patent: 6773996 (2004-08-01), Suzawa et al.
patent: 6790749 (2004-09-01), Takemura et al.
patent: 6809339 (2004-10-01), Suzawa et al.
patent: 7050138 (2006-05-01), Yamazaki et al.
patent: 2002/0006705 (2002-01-01), Suzawa et al.
patent: 2002/0011627 (2002-01-01), Takemura et al.
patent: 2002/0016028 (2002-02-01), Arao et al.
patent: 2003/0006414 (2003-01-01), Takemura et al.
patent: 2003/0032210 (2003-02-01), Takayama et al.
patent: 2004/0018670 (2004-01-01), Arao et al.
patent: 2004/0135216 (2004-07-01), Suzawa et al.
patent: 2004/0263712 (2004-12-01), Yamazaki et al.
patent: 2005/0037549 (2005-02-01), Takemura et al.
patent: 2005/0040403 (2005-02-01), Suzawa et al.
patent: 2005/0052584 (2005-03-01), Yamazaki et al.
patent: 2005/0070038 (2005-03-01), Yamazaki et al.
patent: 6-124962 (1994-05-01), None
patent: 8-250739 (1996-09-01), None
patent: 2001-102585 (2001-04-01), None
patent: 2002-64107 (2002-02-01), None
patent: 2002-83805 (2002-03-01), None
patent: 2003-174153 (2003-06-01), None
Maeguchi et al., “5. TiSi2CoSi2, NiSi”, Innovation in Logic LSI Technology, Science Forum, Aug. 10, 1995, pp. 238-241.

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