Balanced bitcell for a multi-port register file

Details Balanced bitcell for a multi-port register file Balanced bitcell for a multi-port register file

2007-10-09

2007-10-09

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C365S051000, C365S063000, C365S154000, C365S189030, C365S189050, C365S190000, C365S202000, C365S206000, C365S214000, C365S230050, C365S230060

Reexamination Certificate

active

11042026

ABSTRACT:
In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

REFERENCES:
patent: 5289427 (1994-02-01), Nicholes et al.
patent: 5812486 (1998-09-01), Shinmori
Chinese language office action dated Mar. 2, 2007.

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