Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11167523
ABSTRACT:
The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.
REFERENCES:
patent: 2002/0175705 (2002-11-01), Lowy et al.
A. Salz and M.A. Horowitz, “IRSIM: An Incremental MOS Switch-Level Simulator”, Proceedings of the Design Automation Conference, Jun. 1989, pp. 173-178.
Randal E. Bryant, “Extraction Of Gate Level Models From Transistor Circuits By Four-Valued Symbolic Analysis”, International Conference on Computer-Aided Design (ICCAD '91), 1991, pp. 1-8.
J. Grodstein et al., “Automatic Detection Of MOS Synchronizers For Timing Verification”, Computer-Aided Design, ICCAD-91, Digest of Technical Papers, IEEE International Conference on Nov. 11-14, 1991, pp. 304-307.
C. McDonald and R. Bryant, “Symbolic Functional And Timing Verification Of Transistor-Level Circuits”, Computer-Aided Design, Digest of Technical Papers, IEEE/ACM International Conference on Nov. 7-11, 1999, pp. 526-530.
Dastidar Tathagato Rai
Ray Partha
Yashfe Amir
Do Thuan
National Semiconductor Corporation
Pickering Mark C.
LandOfFree
Method of identifying state nodes at the transistor level in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of identifying state nodes at the transistor level in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of identifying state nodes at the transistor level in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3824172