MOSFET with high angle sidewall gate and contacts for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S412000, C257S368000, C257S408000, C257S409000, C257SE21574, C257SE27029

Reexamination Certificate

active

11162424

ABSTRACT:
The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

REFERENCES:
patent: 4182023 (1980-01-01), Cohen et al.
patent: 4394182 (1983-07-01), Maddox, III
patent: 4675715 (1987-06-01), Lepselter et al.
patent: 6531724 (2003-03-01), Furukawa et al.
patent: 6858903 (2005-02-01), Natzle et al.
Bana “A Method for Estimating Overlap Capacitance in Mosfet Devices by DC Current Measurement”, http://sunsite.berkeley.edu/TechRepPages/ERL-93-77, last update Mar. 3, 2005, pp. 1-2.
“MOS Field-Effect Transistor”, http://qucs.sourceforge.net/tech
ode29.html; last update Mar. 3, 2005; pp. 1-13.

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