Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-06-12
2007-06-12
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000, C714S734000, C714S030000, 72
Reexamination Certificate
active
10754455
ABSTRACT:
The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.
REFERENCES:
patent: 5638383 (1997-06-01), Wotzak et al.
patent: 6505313 (2003-01-01), Phan et al.
patent: 6574763 (2003-06-01), Bertin et al.
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6651202 (2003-11-01), Phan
patent: 6668348 (2003-12-01), Nakamura
patent: 6721215 (2004-04-01), Le et al.
patent: 6769081 (2004-07-01), Parulkar
patent: 6871297 (2005-03-01), Puri et al.
patent: 6907555 (2005-06-01), Nomura et al.
patent: 7047465 (2006-05-01), Trimberger
patent: 2001/0054166 (2001-12-01), Fukuda
patent: 2004/0006729 (2004-01-01), Pendurkar
patent: WO 02/25957 (2002-03-01), None
F. Karimi & F. Lombardi, “A Scan-Bist Environment for Testing Embedded Memories”, IEEE Computer Cosiety, 1087-4852/02, all pages (no page numbers thus entire document, 7 pages in all).
Bai Hong Fang and Nicola Nicolici, “Power-Constrained Embedded Memory BIST Architecture”, IEEE Computer Cosiety, 1063-6722/03, all pages (no page numbers thus entire document, 8 pages in all).
Examination Report dated Mar. 29, 2004.
English Translation of Examination Report dated Mar. 29, 2004.
Beer Peter
Ohlhoff Carsten
De'cady Albert
Infineon - Technologies AG
Radosevich Steven D.
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