Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-06-26
2007-06-26
Le, Thao X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S438000, C438S623000, C438S626000, C438S631000, C438S508000
Reexamination Certificate
active
11166970
ABSTRACT:
The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers (8) to (12) are adapted so that photo-lithographic processing is implemented to a first insulating layer (22) formed by photosensitive insulating resin material to form via hole grooves (25), and photo-lithographic processing is implemented to a second insulating layer (23) formed by photosensitive insulating resin material on the first insulating layer (22) to form wiring grooves (27). A conductive metal layer (24) is formed on the second insulating layer (23) in such a manner that conductive metal is filled within the via hole grooves (25) and the wiring grooves (27) to implement polishing processing to the conductive metal layer (24) until the principal surface of the second insulating layer (23) is exposed to form via holes (13) and wiring patterns (26) by the conductive metal filled within the via hole grooves (25) and the wiring grooves (27).
REFERENCES:
patent: 4336088 (1982-06-01), Hetherington et al.
patent: 5231751 (1993-08-01), Sachdev et al.
patent: 6399897 (2002-06-01), Umematsu et al.
patent: 6400576 (2002-06-01), Davidson
patent: 6577490 (2003-06-01), Ogawa et al.
patent: 6591491 (2003-07-01), Fujii et al.
patent: 6638854 (2003-10-01), Homma et al.
patent: 6881662 (2005-04-01), Kung et al.
patent: 6904674 (2005-06-01), Mune et al.
patent: 6958544 (2005-10-01), Sunohara
patent: 2003/0044588 (2003-03-01), Komoto et al.
patent: 2004/0119166 (2004-06-01), Sunohara
patent: 2004/0227222 (2004-11-01), Kikuchi et al.
patent: 1 137 060 (2001-09-01), None
patent: 2000-261141 (2000-09-01), None
patent: 2001-267747 (2001-09-01), None
patent: 2002-164467 (2002-06-01), None
Depke Robert J.
Le Thao X.
Rockey, Depke, Lyons & Kitzinger LLC
Sony Corporation
LandOfFree
Multi-layer interconnection circuit module and manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-layer interconnection circuit module and manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer interconnection circuit module and manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3813361