Minimum delay buffering method, minimum delay buffer device...

Details Minimum delay buffering method, minimum delay buffer device... Minimum delay buffering method, minimum delay buffer device...

2007-05-08

2007-05-08

Tran, Thang V. (Department: 2627)

Dynamic information storage or retrieval

Control of storage or retrieval operation by a control...

Control of information signal processing channel

Reexamination Certificate

active

10255335

ABSTRACT:
A pattern buffer apparatus for a dynamic write strategy, which buffers non return to zero (NRZ) data patterns in order to generate a recording pulse in a compact disc system, includes a pattern detector which detects a pattern edge and a pattern from the NRZ data; a write address generating unit which generates a write address indicating a pattern buffer which stores the pattern in response to a write enable signal; the pattern buffer which has a plurality of registers and stores the detected pattern according to the write address; and a read address generating unit which generates a read address in response to a read enable signal, and reads the current pattern stored in the pattern buffer indicated by the read address.

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patent: 6044055 (2000-03-01), Hara
patent: 6381206 (2002-04-01), Maeda
patent: 6741531 (2004-05-01), Ueki
patent: 2003/0090971 (2003-05-01), Gushima et al.

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