Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2007-02-13
2007-02-13
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S026000, C375S316000
Reexamination Certificate
active
11022291
ABSTRACT:
In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 4992677 (1991-02-01), Ishibashi et al.
patent: 5014226 (1991-05-01), Horstmann et al.
patent: 5036525 (1991-07-01), Wong
patent: 5122690 (1992-06-01), Bianchi
patent: 5465093 (1995-11-01), Kusumoto et al.
patent: 5546424 (1996-08-01), Miyake
patent: 5596285 (1997-01-01), Marbot et al.
patent: 5668830 (1997-09-01), Georgiou et al.
patent: 5742798 (1998-04-01), Goldrian
patent: 5757297 (1998-05-01), Ferraiolo et al.
patent: 5778217 (1998-07-01), Kao
patent: 5877647 (1999-03-01), Vajapey et al.
patent: 5898321 (1999-04-01), Ilkbahar et al.
patent: 6288563 (2001-09-01), Muljono et al.
patent: 6380758 (2002-04-01), Hsu et al.
patent: 6448806 (2002-09-01), Roth
patent: 6509756 (2003-01-01), Yu et al.
patent: 6541966 (2003-04-01), Rosenfield et al.
patent: 6707325 (2004-03-01), Taguchi et al.
patent: 6760389 (2004-07-01), Mukherjee et al.
patent: 6839861 (2005-01-01), Hoke et al.
patent: 6885691 (2005-04-01), Lyu
patent: 6897712 (2005-05-01), Ficken et al.
patent: 6979987 (2005-12-01), Kernahan et al.
patent: 7092472 (2006-08-01), Stojanovic
patent: 2004/0203559 (2004-10-01), Stojanovic et al.
patent: 2000-35831 (2000-02-01), None
Hoke et al., Self-timed interface for S/390 I/O subsystem interconnection, International Business Machines Corporation, J. Res. Develop. vol. 43 No. 5/6, Sep./Nov. 1999.
J.M. Hoke et al, sef-timed Interface for S/390 I/O Subsystem Interconntion, IBM J. Res. Develop., vol. 43, No. 5/6, Sep./Nov. 1999, pp. 829-846.
Scott C. Douglas, “Fast Implementatiosn of the Filtered-X LMS and LMS Algorithms for Multichannel Active Noise Control,”IEEE Transactions on Speech and Audio Proc., vol. 7, No. 4, Jul. 1999, pp. 454-465.
Chen-Chu Yeh and John R. Barry, “Adaptive Minimum Bit-Error Rate Equalization for Binary Signaling,”IEEE Transactions on Communications, vol. 48, No. 7, Jul. 2000 pp. 1226-1235.
Vladimir Stojanovic, George Ginis and Mark A. Horowitz, “Transmit Pre-emphasis for High-Speed Time-Division-Multiplexed Serial-Link Transceiver,” International Conference on Communications, New York, NY, May 2, 2002, pp. 1-6.
Ho Andrew
Stojanovic Vladimir M.
Rambus Inc.
Shemwell Mahamedi LLP
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