Arrangement for generating a decoder clock signal

Details Arrangement for generating a decoder clock signal Arrangement for generating a decoder clock signal

2007-05-22

2007-05-22

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000

Reexamination Certificate

active

10180402

ABSTRACT:
The invention relates to an arrangement for generating a decoder clock signal for decoding a data signal which is available together with a clock signal and a data word signal signalizing data words, both of which signals may each have different frequencies. The arrangement comprises a phase control circuit (1) which receives the clock signal and supplies the decoder clock signal from its output, and which comprises at least one adjustable divider (14) which is preferably arranged at the input of the phase control circuit (1) and whose division ratio is adjustable.

REFERENCES:
patent: 5703537 (1997-12-01), Bland et al.
patent: 6151479 (2000-11-01), Kummer
patent: 6522278 (2003-02-01), Rhode et al.
patent: 6531975 (2003-03-01), Trotter et al.

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