Semiconductor memory device storing part of program...

Details Semiconductor memory device storing part of program... Semiconductor memory device storing part of program...

2007-01-09

2007-01-09

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S154000, C712S205000

Reexamination Certificate

active

10686724

ABSTRACT:
An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.

REFERENCES:
patent: 5381533 (1995-01-01), Peleg et al.
patent: 6684319 (2004-01-01), Mohamed et al.
patent: 2004/0128476 (2004-07-01), Nuckolls et al.
patent: 9-319657 (1997-12-01), None
patent: 10-340228 (1998-12-01), None
“Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications”, by Preeti Ranjan Panda et al., European Design and Test Conference, Mar. 1997.

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