Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-02-13
2007-02-13
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S031000, C326S032000, C324S601000, C333S017300
Reexamination Certificate
active
11113868
ABSTRACT:
Disclosed is an on-die termination (‘ODT’) impedance calibration device. The ODT impedance calibration device comprises: a pulse generator for outputting a calibration signal of a pulse type for calibrating an ODT impedance; an M-bit counter for counting the number of pulses of the calibration signal; a first maximum counter trigger signal generator controlled by the M-bit counter; an N-bit counter for counting the number of pulses of the calibration signal; a second maximum counter trigger signal generator controlled by the N-bit counter; a delay unit for receiving a delay signal and outputting the delay signal after a predetermined period of time; an update trigger signal generator for outputting a pulse signal which is toggled according to an output signal of the delay unit; and an ODT impedance calibration unit for receiving the calibration signal and outputting a control signal for calibrating an ODT impedance.
REFERENCES:
patent: 6307424 (2001-10-01), Lee
patent: 6624659 (2003-09-01), Abraham et al.
patent: 6924660 (2005-08-01), Nguyen et al.
patent: 6980020 (2005-12-01), Best et al.
Cho Seong Ik
Park Nak Kyu
Barnie Rexford
Crawford Jason
Hynix / Semiconductor Inc.
Ladas & Parry LLP
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