Semiconductor memory device for storing data as state of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S314000, C257S316000

Reexamination Certificate

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10994629

ABSTRACT:
A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.

REFERENCES:
patent: 5350938 (1994-09-01), Matsukawa et al.
patent: 6111286 (2000-08-01), Chi et al.
patent: 6734490 (2004-05-01), Esseni et al.
patent: 2006/0246605 (2006-11-01), Jung et al.
patent: 2003-68877 (2003-03-01), None
Takashi Ohsawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
S. Okhonin, et al., “A Capacitor-Less 1T-DRAM Cell”, IEEE Electron Device Letters, vol. 23, No. 2, Feb. 2002, pp. 85-87.
U.S. Appl. No. 10/617,391, filed Jul. 11, 2003, Ikehashi.
U.S. Appl. No. 10/994,629, filed Nov. 23, 2004, Nakajima, et al.

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