Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-02-20
2007-02-20
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S928000, C438S667000, C438S678000
Reexamination Certificate
active
10985757
ABSTRACT:
An apparatus comprising an insulating substrate (101) having first and second surfaces (101a, 101b) and a plurality of metal-filled vias (102) extending from the first to the second surface. The first and second surfaces have contact pads (103, 104), each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer (110, copper) in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer (111a, copper) secured to the seed metal layer, a second electroplated support layer (111b, nickel), and at least one reflow metal bonding layer (112, palladium, gold) on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors (220, 230) provide attachment to chip contact pads and external parts.
REFERENCES:
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5169680 (1992-12-01), Ting et al.
patent: 5707893 (1998-01-01), Bhatt et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6426011 (2002-07-01), Katoh
patent: 6620731 (2003-09-01), Farnworth et al.
patent: 6683380 (2004-01-01), Efland et al.
patent: 6852625 (2005-02-01), Shin et al.
patent: 6872590 (2005-03-01), Lee et al.
patent: 6915566 (2005-07-01), Abbott et al.
patent: 6924224 (2005-08-01), Egitto et al.
patent: 6936536 (2005-08-01), Sinha
patent: 6964887 (2005-11-01), Akagawa
patent: 7022609 (2006-04-01), Yamamoto et al.
patent: 7034401 (2006-04-01), Savastiouk et al.
patent: 2001/0033020 (2001-10-01), Stierman et al.
patent: 2002/0192939 (2002-12-01), Sugihara
patent: 2004/0113244 (2004-06-01), Shin et al.
patent: 2004/0124535 (2004-07-01), Chang
patent: 2004/0132279 (2004-07-01), Egitto et al.
patent: 2004/0166661 (2004-08-01), Lei
patent: 2006/0145359 (2006-07-01), Sunohara et al.
patent: 2006/0199383 (2006-09-01), Tachibana
Brady III Wade James
Tung Yingsheng
Wilczewski M.
LandOfFree
Semiconductor assembly having substrate with electroplated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor assembly having substrate with electroplated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor assembly having substrate with electroplated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3808816