Multi-ported register files

Details Multi-ported register files Multi-ported register files

2007-04-03

2007-04-03

Tran, M. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S063000

Reexamination Certificate

active

10330652

ABSTRACT:
A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.

REFERENCES:
patent: 5777928 (1998-07-01), Vidwans et al.
patent: 2004/0120182 (2004-06-01), Biyani et al.
patent: 2005/0216698 (2005-09-01), Chu et al.
Krishnamurthy, Ram, et al., “A 0.13 μm 6GHz 256×32b Leakage-tolerant Register File”,2001 Symposium on VLSI Circuits Digest of Technical Papers, (Jun. 14-16, 2001), 2 pages.
Tang, Stephen, et al., “A Leakage-Tolerant Dynamic Register File Using Leakage Bypass with Stack Forcing (LBSF) and Source Follower NMOS (SFN) Techniques”,2002 Symposium on VLSI Circuits Digest of Technical Papers, (Jun. 13-15, 2002), 2 pages.

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