Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-04-24
2007-04-24
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S152000, C714S015000
Reexamination Certificate
active
10703279
ABSTRACT:
An improved program status register is disclosed with a feature to handle state change for a processor and its memory subsystem. The program status register comprises a clock, at least one update value for updating the program status register to a second value from a first value when an update enable signal is received, a sampled program status register storing the first value of the program status register, and a state change sampling register generating a synchronized state change signal from a state change indication signal and the clock. When the update enable signal is initially received and a state change indication signal is further received thereafter during a first clock cycle, an updated output of the program status register is restored through a first selection module triggered by the synchronized state change signal to the first value in a second clock cycle following the first clock cycle.
REFERENCES:
patent: 5682492 (1997-10-01), McFarland et al.
patent: 5701493 (1997-12-01), Jaggar
patent: 5758112 (1998-05-01), Yeager et al.
Frazier, Tiffany et al., Execution-Driven Simulation of Error Recovery Techniqes for Multicomputers, Apr. 7-9, 1997, Simulation Symposium, pp. 4-13.
Miller William V.
Patchen Paul J.
Butler Dennis M.
Connolly Mark
Preston Gates & Ellis LLP
VIA Technologies, Inc. of Taiwan
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