Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-04-24
2007-04-24
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S168000, C711S169000
Reexamination Certificate
active
11281184
ABSTRACT:
A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
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Rambus, Inc. Data Sheet, Preliminary Information, 8/9-Mbit (1M×8/9) and 16/
Hampel Craig E.
Perego Richard E.
Tsern Ely K.
Ware Frederick A.
Nguyen T
Rambus Inc.
Shemwell Mahamedi LLP
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