Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-05-01
2007-05-01
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S175000
Reexamination Certificate
active
11158396
ABSTRACT:
A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.
REFERENCES:
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 5130777 (1992-07-01), Galbraith et al.
patent: 5278839 (1994-01-01), Matsumoto et al.
patent: 5313425 (1994-05-01), Lee et al.
patent: 5432729 (1995-07-01), Carson et al.
patent: 5469450 (1995-11-01), Cho et al.
patent: 5498979 (1996-03-01), Parlour et al.
patent: 5579265 (1996-11-01), Devin
patent: 5642318 (1997-06-01), Knaack et al.
patent: 5701267 (1997-12-01), Masuda et al.
patent: 5708667 (1998-01-01), Hayashi
patent: 5748545 (1998-05-01), Lee et al.
patent: 5751647 (1998-05-01), O'Toole
patent: 5757700 (1998-05-01), Kobayashi
patent: 5784391 (1998-07-01), Konigsburg
patent: 5796694 (1998-08-01), Shirane
patent: 5831989 (1998-11-01), Fujisaki
patent: 5835396 (1998-11-01), Zhang
patent: 5835509 (1998-11-01), Sako et al.
patent: 5872790 (1999-02-01), Dixon
patent: 5909049 (1999-06-01), McCollum
patent: 5920502 (1999-07-01), Noda et al.
patent: 5943254 (1999-08-01), Bakeman, Jr. et al.
patent: 5986950 (1999-11-01), Joseph
patent: 6016269 (2000-01-01), Peterson et al.
patent: 6026476 (2000-02-01), Rosen
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6205564 (2001-03-01), Kim et al.
patent: 6216247 (2001-04-01), Creta et al.
patent: 6236587 (2001-05-01), Gudesen et al.
patent: 6407953 (2002-06-01), Cleeves et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6438044 (2002-08-01), Fukuda
patent: 6446242 (2002-09-01), Lien et al.
patent: 6462988 (2002-10-01), Harari
patent: 6487749 (2002-12-01), Tsui
patent: 6498749 (2002-12-01), Cuppens et al.
patent: 6515923 (2003-02-01), Cleeves
patent: 6525953 (2003-02-01), Johnson
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6574145 (2003-06-01), Kleveland et al.
patent: 6591394 (2003-07-01), Lee et al.
patent: 6597595 (2003-07-01), Ichiriu et al.
patent: 6658438 (2003-12-01), Moore et al.
patent: 6661730 (2003-12-01), Scheuerlein et al.
patent: 6728126 (2004-04-01), Issaq et al.
patent: 6728149 (2004-04-01), Akamatsu
patent: 6868022 (2005-03-01), Scheuerlein et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0085431 (2002-07-01), Jeon et al.
patent: 2002/0162062 (2002-10-01), Hughes et al.
patent: 2003/0021176 (2003-01-01), Hogan
patent: 2003/0115514 (2003-06-01), Ilkbahar et al.
patent: 2003/0115518 (2003-06-01), Kleveland et al.
patent: 2003/0120858 (2003-06-01), March et al.
patent: 2004/0100831 (2004-05-01), Johan et al.
patent: 2004/0255089 (2004-12-01), Unno
patent: 2005/0044459 (2005-02-01), Scheuerlein et al.
patent: 2005/0078537 (2005-04-01), So et al.
patent: 2 265 031 (1993-09-01), None
“A 16Mb Mask ROM with Programmable Redundancy,” Nsruka et al., ISSCC 1989/Session 10: Nonvolatile Memories/Paper THAM 10.1, 2 pages, Feb. 16, 1989.
“Circuit Technologies for 16 Mb DRAMs,” Mano et al., ISSCC 1987/Session 1: MEGABIT DRAMs/Paper WAM 1.6, 2 pages, Feb. 27, 1987.
“Memory Device and Method for Storing and Reading Data in a Write-Once Memory Array,” U.S. Appl. No. 09/877,720, filed Jun. 8, 2001; inventors: Christopher S. Moore, James E. Schneider, J. James Tringali and Roger W. March.
“Memory Device and Method for Storing and Reading a File System Structure in a Write-Once Memory Array,” U.S. Appl. No. 09/877,719, filed Jun. 8, 2001; inventors: Christopher S. Moore, James E. Schneider, J. James Tringali and Roger W. March.
“Method for Reading Data in a Write-Once Memory Device Using a Write-Many File System,” U.S. Appl. No. 09/818,138, filed Jun. 8, 2001; inventors: J. James Tringali, Christopher S. Moore, Roger W. March, James E. Schneiger, Derek Bosch, and Daniel C. Steere.
“Method for Re-Directing Data Traffic in a Write-Once Memory Device,” U.S. Appl. No. 09/877,691, filed Jun. 8, 2001; inventors: James J. Tringali, Christopher S. Moore, Roger W. March, James E. Schneider, Derek Bosch, and Daniel C. Steere.
“Method for Making a Write-Once Memory Device Read Compatible with a Write-Many File System,” U.S. Appl. No. 10/023,468, filed Dec. 14, 2001; inventors: Christopher S. Moore, Matt Fruin, Colm Lysaght, and Roy E. Scheuerlein.
“Reed-Solomon Codes: An introduction to Reed-Solomon Codes: principles, architecture and implementation,” http://www.4i2i.com/reed solomon codes.htm, 8 pages.
“TP 9.2: A 30ns 64Mb DRAM with Build-in-Self-Test and Repair Function,” ISSCC 92 Session 9/Non-Volatile and Dynamic Rams/Paper 9.2, 2 pages, 1992.
“64M x 8 Bit, 32M x 16 Bit NAND Flash Memory,” Samsung Electronics, 39 pages.
“Exotic memories, diverse approaches,” 8 pages, www.ednasia.com, Sep. 2001.
“A Vertical Leap for Microchips: Engineers have discovered a way to pack more computing power into microcircuits: build them vertically as well as horizontally,” Thomas H. Lee, 8 pages.
“Three-Dimensional Memory Array and Method of Fabrication,” U.S. Appl. No. 09/560,626, filed Apr. 28, 2000; inventors: Johan Knall.
Zhang et al., “On-state reliability of amorphous silicon antifuses,” IEDM Digest of Technical Papers, pp. 551-554, 1995.
Shih et al., “Characterization and modeling of a highly reliable metal-to-metal antifuse for high-performance and high-density field-programmable gate arrays,” Proceedings of IEEE, Int. Reliability Physics Synp., 1997, pp. 25-33.
“Method and Apparatus for Improving Yield in Semiconductor Devices at Guaranteeing Health of Redundancy Information,” U.S. Appl. No. 11/024,516, filed Dec. 28, 2004, Inventors: Alper Ilkbahar and Derek J. Bosch.
International Search Report and Written Opinion for PCT/US2006/023107, 12 pages, Nov. 17, 2006.
Kleveland Bendik
Lee Tae Hee
Li Feng
Yang Chia
Yang Xiaoyu
Auduong Gene N.
Brinks Hofer Gilson & Lione
SanDisk 3D LLC
LandOfFree
Method and apparatus for programming a memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for programming a memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for programming a memory array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3801890