Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-05-29
2007-05-29
Myers, Paul R. (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C710S313000, C370S252000, C370S257000
Reexamination Certificate
active
10179317
ABSTRACT:
In lieu of a strictly dedicated bus transaction such as a ping and self-identification, the timing delays for an IEEE 1394 serial bus are determined by an asynchronous transaction request and responsive acknowledgement response. Timing may therefore be determined either from asynchronous transactions occurring for other purposes (e.g., a read or write) or initiated for the purpose of determining timing.
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Koninklijke Philips Electronics , N.V.
Liberchuk Larry
Myers Paul R.
Stiglic Ryan
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