Integrated circuit device having non-linear active area pillars

Details Integrated circuit device having non-linear active area pillars Integrated circuit device having non-linear active area pillars

2007-05-29

2007-05-29

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S318000, C257S365000

Reexamination Certificate

active

11287038

ABSTRACT:
An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to form word lines that intersect the active area lines at the angled segments.

REFERENCES:
patent: 6410948 (2002-06-01), Tran et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 2005/0023633 (2005-02-01), Yeo et al.
patent: WO 2004/038770 (2004-05-01), None
C.H. Lee, et al., Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and beyond, 2004 Symposium on VLSI Technology Digest of Technical Papers.
F. Fishburn, et al., A 78nm 6F2DRAM Technology for Multigigabit Densities, 2004 Symposium on VLSI Technology Digest of Technical Papers.
R. Katsumata, et al., Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM, 2003 Symposium on VLSI Technology Digest of Technical Papers.
T. Park, et al., Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers, 2003 Symposium on VLSI Technology Digest of Technical Papers.

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