Semiconductor memory device having redundancy cell array...

Details Semiconductor memory device having redundancy cell array... Semiconductor memory device having redundancy cell array...

2007-04-24

2007-04-24

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S145000

Reexamination Certificate

active

10879100

ABSTRACT:
A semiconductor memory device includes memory cell arrays, a redundancy cell array shared by the memory cell arrays, a correction capacitance, and switching circuits arranged in correspondence with the memory cell arrays. Each memory cell array includes ferroelectric cells arranged at the intersections between word lines and bit lines. The redundancy cell array includes spare ferroelectric cells arranged at the intersections between spare word lines and redundancy bit lines. The number of spare ferroelectric cells connected to the redundancy bit line is smaller than that of ferroelectric cells connected to the bit line in each memory cell array. The correction capacitance is connected to the redundancy bit line to make its capacitance equivalent to that of the bit line. When a replaced ferroelectric cell in the memory cell array is selected, the switching circuits select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell.

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Daisaburo Takashima, et al., A 76mm28Mb Chain Ferroelectric Memory, Non-Volatile Memories, ISSCC 2001, Session 2, 2.7, pp. 40-41.

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