Stress-reduced layer system for use in storage capacitors

Details Stress-reduced layer system for use in storage capacitors Stress-reduced layer system for use in storage capacitors

2007-04-03

2007-04-03

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000

Reexamination Certificate

active

10780075

ABSTRACT:
The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

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K. Yamada et al.: “A Deep-Trenched Capacitator Technology For 4 Mega Bit Dynamic RAM”, Proceedings of International Devices and Materials, IEDM 85, 1985, pp. 702-705.

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