Clock distribution circuit

Details Clock distribution circuit Clock distribution circuit

2007-04-17

2007-04-17

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000

Reexamination Certificate

active

10127297

ABSTRACT:
A user circuit unit is configured by a gate array, a PLL circuit is configured in a microprocessor macro unit, a clock frequency output from the PLL circuit in the microprocessor macro unit is directly distributed to a user circuit unit (CLK3), and the clock frequency distributed to the user circuit unit is distributed to the microprocessor macro unit through a frequency divider configured by the user circuit unit.

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