Method of verifying a system in which a plurality of master...

Details Method of verifying a system in which a plurality of master... Method of verifying a system in which a plurality of master...

2007-04-24

2007-04-24

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S146000, C711S154000

Reexamination Certificate

active

11331145

ABSTRACT:
In logical verification of a system in which a plurality of master devices share a storage region, a scoreboard common to all master devices is provided. When starting verification, an initial value of data stored in each address of each storage device is set in correspondence with the address in the scoreboard. When each master device performs write access to an address of a storage device, data corresponding to the address in the scoreboard is updated with written data. When each master device performs read access to an address of a storage device, data read out of the storage device is compared with data corresponding to the address in the scoreboard. Thus, the storage devices and the controller are verified.

REFERENCES:
patent: 5809294 (1998-09-01), Ando
patent: 6260135 (2001-07-01), Yoshida

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