Semiconductor memory device and timing control method

Details Semiconductor memory device and timing control method Semiconductor memory device and timing control method

2007-01-09

2007-01-09

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S200000

Reexamination Certificate

active

10943000

ABSTRACT:
A semiconductor memory device for suitably controlling the timing for accessing data in a memory cell. The semiconductor memory device includes a memory cell. A bit line, connected to the memory cell, is used to access data stored in the memory cell. A first path for generating a first timing signal includes a dummy cell for storing data. A dummy bit line, connected to the dummy cell, is used to access the data stored in the dummy cell. A second path for generating a second timing signal has a delay characteristic differing from that of the first path. A control circuit controls the timing for accessing the data stored in the memory cells using one of the first timing signal and the second timing signal.

REFERENCES:
patent: 6172916 (2001-01-01), Ooishi
patent: 6201757 (2001-03-01), Ward et al.
patent: 6410379 (2002-06-01), Wahlstrom
patent: 6646938 (2003-11-01), Kodama
patent: 2002-109887 (2002-04-01), None

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