VPA logic circuits

Details VPA logic circuits VPA logic circuits

2007-03-20

2007-03-20

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000, C326S041000, C716S030000, C257S774000

Reexamination Certificate

active

10882579

ABSTRACT:
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5329498 (1994-07-01), Greenstein
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815372 (1998-09-01), Gallas
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 5982655 (1999-11-01), Doyle
patent: 6002991 (1999-12-01), Conn, Jr.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6233191 (2001-05-01), Gould et al.
patent: 6292019 (2001-09-01), New et al.
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6515505 (2003-02-01), Rees
patent: 6515509 (2003-02-01), Baxter
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642744 (2003-11-01), Or-Bach et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6831479 (2004-12-01), Lo
patent: 6838902 (2005-01-01), Elftmann et al.
patent: 6992505 (2006-01-01), Zhou
patent: 7030651 (2006-04-01), Madurawe
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0196066 (2004-10-01), Ting
U.S. Appl. No. 10/882,583, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,276, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,486, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/882,946, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/882,839, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,213, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,051, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/882,583, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,276, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,486, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/882,946, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/882,839, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,213, filed Jun. 30, 2004, Schmit.
U.S. Appl. No. 10/883,051, filed Jun. 30, 2004, Schmit.
“§3 Programmable Logic Devices,”Digital System Design, 2001, pp. 3.1-3.28, Month N/A.
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8.
“The Effect of SRAM Table Sharing and Cluster Size on FPGA Area”, pp. 1-10, Date N/A.
“The Xilinx Virtex Series FPGA,” Jan. 22, 2001, slides 1-22.
“Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture,” ISCA '04, 2004, ACM, Munchen, Oberbayern, Germany, Month N/A.
Agrawal, O., et al., “An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions,”FPGA 99, 1999, pp. 17-26, ACM, Monterey, Ca, USA, Month N/A.
Ahmed, E., et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,”FPGA 2000, 2000, ACM, Monterey, CA, USA, Month N/A.
ALTERA CORP., “6. DSP Blocks in Stratix II Devices,” SII52006-1.0, Feb. 2004, pp. 1-32.
ALTERA, “Stratix II DSP Performance,”White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA.
Backus, J., “Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs,”Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, No. 8, ACM.
Barker, R., “QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set,”A Technology Application Whitepaper, 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, Month N/A.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 487-494, IEEEE, Month N/A.
Camposano, R., “The Growing Semiconductor Zoo: ASICs, CSSP, ASSP. ASIP. Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” 2003, pp. 1-74, Synopsys, Inc., Month N/A.
Caspi, E., et al., “A Streaming Multi-Threaded Model,”MSP-3, Dec. 2, 2001, pp. 1-23.
Caspi, E., et al., “Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.
Compton, K., et al., “An Introduction to Reconfigurable Computing,”, date N/A.
Compton, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,”ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, NY.
Cong, J., et al., “Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,”ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc.
Davare, A., et al., “The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications,”DAC '04, Jun. 7-11, 2004, ACM, San Diego, California, USA.
Dehon, A., Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization). pp. 1-10. (Applicants believe that this article also appears inProceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-13

Affiliated with

Also associated with

Rating

VPA logic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with VPA logic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and VPA logic circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3788118