Layout structure for memory arrays with SOI devices

Details Layout structure for memory arrays with SOI devices Layout structure for memory arrays with SOI devices

2007-07-31

2007-07-31

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S069000, C257S903000

Reexamination Certificate

active

11078745

ABSTRACT:
A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area is formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of a passing gate transistor and a pull-down transistor used in an SRAM cell. The strapping cell area is interposed between the SRAM cell areas, in which a strapping cell is constructed for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor constructed on the OD area from floating.

REFERENCES:
patent: 5619056 (1997-04-01), Kuriyama et al.
patent: 6646305 (2003-11-01), Assaderaghi et al.
patent: 6747323 (2004-06-01), Komori
patent: 6933578 (2005-08-01), Sato

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