Low power chip select (CS) latency option

Details Low power chip select (CS) latency option Low power chip select (CS) latency option

2007-01-23

2007-01-23

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S191000, C365S233100

Reexamination Certificate

active

11055332

ABSTRACT:
A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle. Thus, activation and deactivation of memory input buffers may be performed without forcing the memory device into power down mode and without employing complex circuits for power management. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

REFERENCES:
patent: 5602798 (1997-02-01), Sato et al.
patent: 5926435 (1999-07-01), Park et al.
patent: 5959930 (1999-09-01), Sakurai
patent: 5986943 (1999-11-01), Isa
patent: 6188641 (2001-02-01), Uchida
patent: 6256260 (2001-07-01), Shim et al.
patent: 6351433 (2002-02-01), Kosugi
patent: 6356489 (2002-03-01), Lee
patent: 6594770 (2003-07-01), Sato et al.
patent: 2005/0157585 (2005-07-01), Kato et al.
H. Heske, article entitled: Mobile RAMs can help save power, Portable Design, Jul. 2002, pp. 1-4, appearing at http://cgw.archives.printthis.clickability.com.
MICRON, Designline, vol. 12, Issue 2, containing article entitled: DDR2 Offers New Features and Functionability, pp. 1-16, available at website http://www.alienware.com/.
product—detail—pages/Area-51/PDFs on Dec. 23, 2004.
MICRON Double Data Rate (DDR) SDRAM specification, pp. 1-84 available at website http://download.micron.com/pdf/datasheets/dram/ddr/.
256MBDDRx4x8x16.pdf on Dec. 27, 2004.

Affiliated with

Also associated with

Rating

Low power chip select (CS) latency option does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power chip select (CS) latency option, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power chip select (CS) latency option will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3786041