Parallel distributed sample descrambling apparatus of...

Details Parallel distributed sample descrambling apparatus of... Parallel distributed sample descrambling apparatus of...

2007-04-17

2007-04-17

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

C370S395100, C375S365000, C380S268000

Reexamination Certificate

active

10317186

ABSTRACT:
Disclosed is a parallel distributed sample descrambling (DSS) apparatus and a method that lowers a clock speed of 622 MHz into ⅛ speed (77.76 MHz) and operates a serial descrambling processing in unit of bit by converting the processing into a parallel descrambling processing in unit of byte, power consumption can thus be reduced and a sufficient timing margin can be secured. The parallel DSS apparatus includes a serial-parallel conversion unit for converting receiving data into parallel data (D[7:0]) and generating a counter signal, a header error check (hereinafter, as HEC) generation unit for generating HEC data of the receiving data by CRC calculation, and abstracting upper two bits of the HEC data, and a descrambling processing unit for performing parallel descrambling of byte module by receiving output signals of the serial-parallel conversion unit and the HEC generation unit.

REFERENCES:
patent: 5241602 (1993-08-01), Lee et al.
patent: 5448640 (1995-09-01), Kim et al.
patent: 6327262 (2001-12-01), Jeong
patent: 6408077 (2002-06-01), Prunier
patent: 6414957 (2002-07-01), Kang et al.
Byeong Gi Lee and Seok Chang Kim, “Low-Rate Parallel Scrambling Techniques for Today's Lightwave Transmission”, IEEE Communications Magazine, Apr. 1995.

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