One transistor flash memory cell

Details One transistor flash memory cell One transistor flash memory cell

2007-03-13

2007-03-13

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S318000, C257S368000, C257S374000, C257SE27014

Reexamination Certificate

active

11081886

ABSTRACT:
An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line13substantially vertically aligned with a buried source bit line14. The memory array separates the columns with deep trenches46that may also be formed into charge pump capacitors.

REFERENCES:
patent: 4979004 (1990-12-01), Esquivel et al.
patent: 5486714 (1996-01-01), Hong
patent: 5635415 (1997-06-01), Hong
patent: 5644532 (1997-07-01), Chang
patent: 5994733 (1999-11-01), Nishioka et al.
patent: 6211012 (2001-04-01), Lee et al.
patent: 6307781 (2001-10-01), Shum
patent: 6327182 (2001-12-01), Shum et al.
patent: 6418060 (2002-07-01), Yang et al.
patent: 6438030 (2002-08-01), Hu et al.
patent: 6559008 (2003-05-01), Rabkin et al.
patent: 6600199 (2003-07-01), Voldman et al.
patent: 6628544 (2003-09-01), Shum et al.
patent: 6667226 (2003-12-01), Pinto et al.
patent: 6693830 (2004-02-01), Hu et al.
patent: 6815311 (2004-11-01), Hong et al.
patent: 6841824 (2005-01-01), Shum
patent: 6844588 (2005-01-01), Cavins et al.
patent: 6864151 (2005-03-01), Yan et al.
patent: 6864530 (2005-03-01), Yoon
patent: 6885080 (2005-04-01), Chen et al.
patent: 6909139 (2005-06-01), Shum et al.
patent: 2001/0000306 (2001-04-01), Yoon et al.
patent: 2002/0000602 (2002-01-01), Lee
patent: 2002/0033516 (2002-03-01), Choi et al.
patent: 2002/0038882 (2002-04-01), Hartmann et al.
patent: 2002/0070402 (2002-06-01), Ichige et al.
patent: 2002/0110973 (2002-08-01), Liou et al.
patent: 2002/0132425 (2002-09-01), Song et al.
patent: 2002/0151188 (2002-10-01), Kamath et al.
patent: 2002/0197795 (2002-12-01), Saito
patent: 2003/0071297 (2003-04-01), Hara et al.
patent: 2003/0080366 (2003-05-01), Tamura
patent: 2003/0162400 (2003-08-01), Chen et al.
patent: 2004/0262669 (2004-12-01), Shum et al.
patent: 2005/0045944 (2005-03-01), Gratz et al.
patent: 0562307 (1993-09-01), None
patent: 02310971 (1990-12-01), None
patent: 04164372 (1992-06-01), None
patent: WO 9736332 (1997-10-01), None
patent: WO 9944238 (1999-09-01), None
patent: WO 0215190 (2002-02-01), None
Kume, Hitoshi, et al., “A 1.28 m Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM,” 992-IEDM 92-991, pp. 24.7.1, 24.7.2 and 24.7.3, 1992.
Kim, K. S., et al., A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories, 0-7803-2700-4, 1995, IEDM 95-263; pp. 11.1.1, 11.1.2, 11.1.3 and 11.1.4.
Chi-Nan Brian Li, et al., “A Novel Uniform-Channel-Program-Erase (UCPE) Flash EEPROM Using an Isolated P-well Structure”, IEEE, 2000 (Apr. 2000) 0-7803-6441-4/00.
Evans Ching-Song Yang, et al., “Novel Bi-Directional Tunneling Program/Erase NOR (BiNOR)-Type Flash EEPROM”, IEEE 1999, 0018-9383/99, vol. 46, No. 6, Jun. 1999, pp. 1294-1296.

Affiliated with

Also associated with

Rating

One transistor flash memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with One transistor flash memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One transistor flash memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3782648