SRAM-compatible memory for correcting invalid output data...

Details SRAM-compatible memory for correcting invalid output data... SRAM-compatible memory for correcting invalid output data...

2007-01-16

2007-01-16

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10659115

ABSTRACT:
Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained from the input data are written in data banks and parity bank, respectively. When invalid data is output from a specific memory bank due to the performance of a refresh operation or other factors, the invalid data are corrected by a data corrector using the parity value written in the parity bank, thus generating output data having the same logic value as the input data. The SRAM-compatible memory prevents a reduction in operation speed due to an internal operation, such as a refresh operation.

REFERENCES:
patent: 4710934 (1987-12-01), Traynor
patent: 2002/0121886 (2002-09-01), Shau
patent: 2003/0086306 (2003-05-01), Takahashi et al.
patent: 2003/0093744 (2003-05-01), Leung et al.
patent: 2005/0044467 (2005-02-01), Leung et al.
patent: 0 238 417 (1987-09-01), None

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