Semiconductor memory device and manufacturing method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C257S508000

Reexamination Certificate

active

11091140

ABSTRACT:
The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections. The present invention can provide a SRAM whose memory cell size is readily reduced without unduly increasing the number of the steps in the manufacturing method thereof. Further, the present invention can improve the α-ray soft error resistance of the SRAM.

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Inohara et al. Highly Scalable and Fully Logic Compatible SRAM Cell Technology with Metal Damascene Process and W Local Interconnect. Symposium on VLSI Technology Digest of Technical Papers pp. 64-65, 1998.
Ootsuka et al. A Novel .20 μm Full CMOS SRAM Cell Using Stacked Cross Couple with Enhanced Soft Error Immunity. IEDM 1998.
Office Action dated Nov. 9, 2005 for corresponding Japanese Patent Application 2002-011504.

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