Method of forming an N channel and P channel finfet device...

Details Method of forming an N channel and P channel finfet device... Method of forming an N channel and P channel finfet device...

2007-03-06

2007-03-06

Dickey, Thomas L. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21442, C257S347000

Reexamination Certificate

active

10831868

ABSTRACT:
A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

REFERENCES:
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Rainey et al. “Demonstration of FinFET CMOS circuits,” Device Research Conference, 2002 60th DRC. Conference Digest, Jun. 24-26, 2002 pp. 47-48.

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