Signal generating circuit capable of generating a validation...

Details Signal generating circuit capable of generating a validation... Signal generating circuit capable of generating a validation...

2007-09-18

2007-09-18

Mis, David (Department: 2817)

Electrical computers and digital data processing systems: input/

Input/output data processing

Flow controlling

Reexamination Certificate

active

11163899

ABSTRACT:
A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.

REFERENCES:
patent: 5142247 (1992-08-01), Lada, Jr. et al.
patent: 5347232 (1994-09-01), Nishimichi
patent: 5499384 (1996-03-01), Lentz et al.

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