Method of making an electronic package

Details Method of making an electronic package Method of making an electronic package

2007-07-31

2007-07-31

Graybill, David E. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S459000, C438S615000

Reexamination Certificate

active

10282975

ABSTRACT:
A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically shaped caps on the selected copper pads. The partial hemispherically shaped caps are then coated with a solder flux. A thin semiconductor chip with a pattern of conductive elements, corresponding to partial hemispherically shaped capped pads, is then positioned on the substrate so that the conductive elements of the thin semiconductor chip substantially line up with the partial hemispherically shaped capped pads of the substrate. The solder is then heated to reflow temperature and an electrical couple is formed between the thin semiconductor chip and the substrate. Since all the solder necessary to make the electrical couple is positioned on the substrate, it is possible to use a thin semiconductor chip in the electronic package avoiding the problem presented by the handling and processing steps associated with securing a bumped wafer substrate during the thinning process and in subsequent processes of making the thinned semiconductor chip from the bumped wafer, for example, the dicing step.

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