Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-07-24
2007-07-24
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
11000048
ABSTRACT:
A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.
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Nishihara Toshiyuki
Sakai Yoshio
Kananen Ronald P.
Pham Ly Duy
Rader & Fishman & Grauer, PLLC
Sony Corporation
Zarabian Amir
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