Low power NROM memory devices

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185270

Reexamination Certificate

active

11151952

ABSTRACT:
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a charge trapping dielectric layer of the memory cells.

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