Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2007-03-06
2007-03-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S758000
Reexamination Certificate
active
10747938
ABSTRACT:
Provided are a method, system, and program for generating parity data when updating old data stored in an array of storage devices in a data organization type which utilizes parity data. In one embodiment, a logic engine has plural registers or store queues in which new data obtained in a read operation is stored. A logic function such as an Exclusive-OR function is performed on the new data in each of the plural registers using old data obtained in another read operation. A logic function such as an Exclusive-OR function is performed on the intermediate data in one of the plural registers using old parity data of a first type obtained in another read operation, to generate new parity data of the first type. A logic function such as an Exclusive-OR function is performed on the intermediate data in another of the plural registers using old parity data of a second type obtained in another read operation, to generate new parity data of the second type.
REFERENCES:
patent: 5315602 (1994-05-01), Noya et al.
patent: 5537567 (1996-07-01), Galbraith et al.
patent: 5636359 (1997-06-01), Beardsley et al.
patent: 5958067 (1999-09-01), Kaneda et al.
patent: 6151641 (2000-11-01), Herbert
patent: 6247157 (2001-06-01), Edirisooriya
patent: 6353895 (2002-03-01), Stephenson
patent: 6606683 (2003-08-01), Mori
patent: 2005/0050384 (2005-03-01), Horn
patent: 0131456 WO (2003-05-01), None
Patterson, et al. “A Case for Redundant Arrays of Inexpensive Disks (RAID),” 1988 ACM 0-89791-268-3/88/0006/0109; pp. 109-116.
HP Technical Guide, “Mathematics behind RAID 5DP,” Hewlett-Packard Company, 2001; 10 pp.
Intel IOP303 I/O Processor, Internet document http://developer.intel.com/design/iio/80303.htm; copyright 2003, 4 pp. (available prior to Dec. 29, 2003).
Intel IOP331 I/O Processor, Internet document http://developer.intel.com/design/iio/iop331.htm; copyright 2003, 4 pp. (available prior to Dec. 29, 2003).
Intel IOP331I/O Processor Chipset. Internet document http://developer.intel.com/design/iio/docs/iop331.htm; copyright 2003, 1 p. (available prior to Dec. 29, 2003).
Intel 80333 I/O Processor, Developer's Manual. Intel Document No. 305432001US. Copyright Mar. 2005. Copyright & contents (pp. 1-40); Chapters 1 (pp. 41-48) and 6 (pp. 375-408). (subject matter of chapters 1 and 6 available prior to Dec. 29, 2003).
PCT International Search Report and Written Opinion, May 24, 2006, for International Application No. PCT/US2004/043041 (Foreign counterpart for Ser. No. 10/747,932).
RAID ADVISORY BOARD, The RAIDbook, Sixth Edition, Feb. 1997, “Chapter 10: RAID and Cache”, pp. 181-195.
Vilayannur, M., A. Sivasubramaniam, M. Kandemir, R. Thakur, and R. Ross, “Discretionary Caching for I/O on Clusters”, Proceedings of the 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid, May 2003, pp. 96-103.
Official Letter, Nov. 21, 2005, for Republic of China Patent Application No. 93139795 (Foreign Counterpart case for U.S. Appl. No. 10/747,932).
Chaudry Mujtaba
De'cady Albert
Konrad William K.
Konrad Raynes & Victor LLP
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