Efficient memory check architecture and method

Details Efficient memory check architecture and method Efficient memory check architecture and method

2007-07-17

2007-07-17

Maskulinski, Michael (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

10839072

ABSTRACT:
Methods and apparatus are provided for use in testing a memory (230) coupled to a processing node (214). A background scrubber (316) in the processing node (214) is initialized to perform a test of the memory (230). A status of the background scrubber (316) is checked in which the status indicates whether an error occurred during the test. A predetermined action is taken in response to the status indicating that the error occurred during the test.

REFERENCES:
patent: 5673388 (1997-09-01), Murthi et al.
patent: 6158000 (2000-12-01), Collins
patent: 6434696 (2002-08-01), Kang
patent: 7058782 (2006-06-01), Henderson et al.
patent: 2001/0047497 (2001-11-01), Larson et al.
patent: 2004/0230767 (2004-11-01), Bland et al.
“BIOS and Kernel Developer's Guide for AMD Athlon™ 64 and AMD Opteron™ Processors,” AMD Data Sheet, Publication #26094, Revision 3.06; Sec. 3.6 “Function 3—Miscellaneous Control,” 3 pp.; Chapter 5, “Machine Check Architecture,” pp. 143-166.

Affiliated with

Also associated with

Rating

Efficient memory check architecture and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient memory check architecture and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient memory check architecture and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3770685