High performance CMOS transistors using PMD liner stress

Details High performance CMOS transistors using PMD liner stress High performance CMOS transistors using PMD liner stress

2007-03-20

2007-03-20

Tran, Long (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S724000, C438S744000, C438S954000, C257SE23132

Reexamination Certificate

active

10833419

ABSTRACT:
A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

REFERENCES:
patent: 6483172 (2002-11-01), Cote et al.
patent: 6656853 (2003-12-01), Ito
patent: 2004/0253791 (2004-12-01), Sun et al.

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