Memory circuit comprising an error correcting code

Details Memory circuit comprising an error correcting code Memory circuit comprising an error correcting code

2007-09-18

2007-09-18

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S773000

Reexamination Certificate

active

10453844

ABSTRACT:
A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

REFERENCES:
patent: 4604750 (1986-08-01), Manton et al.
patent: 6065146 (2000-05-01), Bosshart
patent: 2003/0188251 (2003-10-01), Brown et al.

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